a. Field of the Invention
The present invention relates to a power amplifier intended mainly for audio signal amplification, and more particularly, it is directed to an improvement of fidelity and power utility in such power amplifier.
b. Description of the Prior Art
A typical arrangement of conventional power amplifiers may be shown as in FIG. 1, wherein the power amplifier comprises: an output stage amplifier circuit for driving a load 7 of the power amplifier; and a driver stage circuit 2 which is illustrated as an operational or a differential amplifier circuit having an inverted input and a non-inverted input and being intended to drive the output stage amplifier circuit. The output stage amplifier circuit is comprised of a complementary symmetry push-pull circuit 3 which comprises a pair of transistors 4 and 5 coupled together at their emitters to form an output terminal 6 of the power amplifier. The amplifier load 7 such as a loud speaker is connected between the output terminal 6 and the ground, i.e. a fixed reference potential of the amplifier circuitry. The bases of the transistors 4 and 5 are coupled together via base biasing current sources 10 and 11 to an output terminal of the driver stage amplifier circuit 2. The collectors of the respective transistors 4 and 5 are supplied with operating voltage from a positive and a negative power source 8 and 9, respectively. Usually, the output terminal 6 is coupled, via a network circuit consisting of, for example, resistors 12 and 13, to the inverted input terminal of the driver stage circuit 2 for the purpose of negative feedback. An input signal (audio signal) applied at the input terminal 1 of the power amplifier is delivered to the non-inverted input of the driver stage circuit 2 to be voltage-amplified, and then it is fed to the output stage amplifier circuit for power amplification.
The transistors 4 and 5 are supplied with base biasing currents by the biasing current sources 10 and 11, respectively, so as to operate in either Class-A or Class-B mode. In the case of Class-B mode operation of the transistors 4 and 5, it is advantageously possible to increase the power utility factor of the complementary symmetry push-pull circuit 3 to a sufficient degree, but the circuit 3 inherently produces cross-over distortion due to the non-linearities of the transistors 4 and 5 at low current condition. In the case of Class-A mode operation of the circuit 3, on the other hand, the foregoing problem represented by cross-over distortion may be obviated, but the power utility factor of the circuit 3 is extermely lowered because of high power loss of the transistors 4 and 5 due to constant flowing of a relatively large amount of idling current. If the collector-emitter voltages of the transistors 4 and 5 are set at a low level, the power utility factor of the circuit 3 may be correspondingly improved, but there will be accompanied by a corresponding reduction in the allowable maximum output of the circuit 3.
As such, the aforementioned conventional arrangement is practically unable to provide a power amplifier having both high power utility factor and high fidelity as well as high output.
One technique of improving the performance of a power amplifier may be found in U.S. Pat. No. 4,115,739 granted on Sept. 19, 1978. According to this known technique, the junction point of the positive and negative power sources 8 and 9 in FIG. 1 of the present application is floated relative to the potential, and this junction point is driven by an additional driver amplifier in accordance with the potential of the amplifier output terminal 6 or input terminal 1. Such an arrangement permits the collector-emitter voltages of the transistors 4 and 5 to be set at a minimum level required for Class-A mode operation of these transistors, so that the output stage amplifier circuit 3 is able to operate at high power utility factor or with high efficiency in Class-A mode also. In this power amplifier, however, the circuit 3 is required to have a sufficient Supply Voltage Rejection Ratio (SVRR) to prevent undesirable effects due to large swinging in that collector potential of the transistors 4 and 5, which potential being varied with the potential of the output terminal of the power amplifier. The SVRR depends not only on the parameters of these transistors 4 and 5, but also it depends on other circuit conditions such as stray capacitance in the circuit 3. Thus, in general, it is not easy to attain a sufficiently good SVRR without substantial complication of the circuit configuration. If the SVRR is at an insufficient level, the operation characteristics of the output stage circuit 3 will be adversely affected by the characteristics of the additional driver amplifier, and thus the operation characteristics will be degraded considerably.